Tier IV has joined the Next-Generation Edge AI Semiconductor Research and Development Program led by the Japan Science and Technology Agency (JST) to advance research and development of a software-defined system-on-chip (SoC) for Level 4 autonomous driving.
Under the JST program, a research team led by Prof. Yoshihiro Kawahara of the Graduate School of Engineering at The University of Tokyo will advance research into use-case-driven, functionally differentiated physical AI chip design. Meanwhile, Tier IV is developing the logic design of an AI chip designed to efficiently process inference for end-to-end (E2E) autonomous driving AI.
“In physical AI applications such as robotics and autonomous driving, GPU power consumption has long been a major bottleneck for deployment on battery-powered devices,” said Prof. Kawahara. “This project aims to fundamentally overcome this constraint through a functionally differentiated chip design backward-mapped from specific use cases.”
High-performance computing technologies, including graphics processing units (GPUs), have played a central role in accelerating the rapid evolution of AI. Level 4 autonomous driving, however, requires AI models to operate continuously under real-world and real-time constraints. This calls for a new approach that complements existing high-performance computing technologies while advancing not only power efficiency but also adaptability, transparency and verifiability.
Tier IV will independently design an AI chip for autonomous driving that supports Autoware, and will evaluate its effectiveness as part of an SoC. In addition to the chip’s logic design, the company will open-source the compiler and related toolchain. By making these technologies available, Tier IV aims to establish an open ecosystem in which semiconductor manufacturers can leverage the firm’s platform technologies to accelerate the commercialization of SoCs for Level 4 autonomous driving.
Power efficiency
Autonomous driving AI increasingly relies on large-scale transformer models that process sensor inputs in an integrated manner from perception through motion planning. This initiative will focus on transformer inference and develop a dedicated architecture that simplifies the complex control mechanisms required for general-purpose computing.
Data required for AI model execution will be efficiently placed in advance and repeatedly reused within the chip, reducing the power consumed by external memory transfers and computation control. The architecture will also incorporate dedicated compute circuits for operations frequently used in transformers, including matrix multiplication and attention mechanisms.
Rather than optimizing only the chip’s peak performance, Tier IV will seek to improve performance per watt across the entire autonomous driving system, including Autoware. The design will support flexible deployment across a broad range of applications, from embedded devices operating at several watts to in-vehicle electronic control units operating at several tens of watts.
Adaptability
The technology surrounding autonomous driving AI is evolving rapidly, making it difficult for architectures designed around a specific model or hardware configuration to adapt continuously to change. To address this challenge, Tier IV will introduce the Tensor Operator Set Architecture (TOSA), a standardized intermediate representation between AI models and the AI chip.
Operations from AI models developed in frameworks such as PyTorch will be converted into a common TOSA representation. Optimization and code generation will then be performed through TOSA before execution on the AI chip, enabling loose coupling between AI frameworks and hardware.
As a result, changes in AI model architectures or computational methods can be accommodated primarily through software updates to components such as the compiler and runtime.
Verifiability
Using TOSA and its clearly defined operator specifications as a foundation, Tier IV will structure the compilation transformation process and introduce formal verification techniques. For selected transformations and operations, the initiative will establish mechanisms to mathematically verify numerical consistency before and after transformation, as well as compliance with predefined error tolerances.
“Through this initiative, we are introducing a software-defined and open approach to AI chip design that combines power efficiency, adaptability, transparency and verifiability,” said Shinpei Kato, the founder and CEO of Tier IV. “In particular, the ability to understand how an AI model is transformed for execution and to verify the correctness of that processing will be increasingly important as autonomous driving systems are deployed in safety-critical environments.”
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